Instruction Set Architecture

Instruction Map

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0x

HALT NOP INT RETI MOV

1x

LDR LDR LDR LDR LDR

2x

LDRH LDRH LDRH LDRH LDRH LDRSH LDRSH LDRSH LDRSH

3x

LDRB LDRB LDRB LDRB LDRB LDRSB LDRSB LDRSB LDRSB

4x

STR STR STR STR

5x

STRH STRH STRH STRH

6x

STRB STRB STRB STRB

7x

ADD SUB MUL UDIV SDIV CMP INC DEC NOT AND NAND OR NOR XOR XNOR

8x

ADD SUB MUL UDIV SDIV CMP AND NAND OR NOR XOR XNOR

9x

STZ STN STC STO STI SHL SHR ROL ROR RCL RCR ASR

Ax

CLZ CLN CLC CLO CLI CLP SHL SHR ROL ROR RCL RCR ASR

Bx

JMP JMPN JMPS JZ JN JC JO JSZ JSN JSC JSO

Cx

JMPA JNZ JNN JNC JNO JSNZ JSNN JSNC JSNO

Dx

JL JLE JG JGE JSL JSLE JSG JSGE

Ex

PUSH PUSH POP PUSHF POPF

Fx

CALL CALLN CALLS CALL RET

Legend: ✅ Completed 🟡 Partialy Complete 🚧 Work In Progress ❌ Not Started

Total Instructions: 130 (390 tasks) - Covered: 102/390 (26.15%)

System Instructions

Opcode	Mnemonic	Impl	Test	Docs
0x00-0x0F	System Instructions
0x00	HALT	✅	✅	❌
0x01	NOP	✅	✅	❌
0x02	INT imm8	🚧	❌	❌
0x03	RETI	🚧	❌	❌
0x08	MOV reg1, reg2	✅	✅	❌
0x10-0x1F	Load Word Instructions
0x10	LDR reg, imm32	✅	✅	❌
0x11	LDR reg1, [reg2]	✅	✅	❌
0x12	LDR reg1, [reg2 + imm16]	✅	✅	❌
0x13	LDR reg1, [reg2 + reg3 * imm8]	✅	✅	❌
0x14	LDR reg1, [imm32]	✅	✅	❌
0x20-0x2F	Load Half Instructions
0x20	LDRH reg, imm32	❌	❌	❌
0x21	LDRH reg1, [reg2]	❌	❌	❌
0x22	LDRH reg1, [reg2 + imm32]	❌	❌	❌
0x23	LDRH reg1, [reg2 + imm32 * imm8]	❌	❌	❌
0x24	LDRH reg1, [imm32]	❌	❌	❌
0x29	LDRSH reg1, [reg2]	❌	❌	❌
0x2A	LDRSH reg1, [reg2 + imm32]	❌	❌	❌
0x2B	LDRSH reg1, [reg2 + imm32 * imm8]	❌	❌	❌
0x2C	LDRSH reg1, [imm32]	❌	❌	❌
0x30-0x3F	Load Byte Instructions
0x30	LDRB reg, imm32	❌	❌	❌
0x31	LDRB reg1, [reg2]	❌	❌	❌
0x32	LDRB reg1, [reg2 + imm32]	❌	❌	❌
0x33	LDRB reg1, [reg2 + imm32 * imm8]	❌	❌	❌
0x34	LDRB reg1, [imm32]	❌	❌	❌
0x39	LDRSB reg1, [reg2]	❌	❌	❌
0x3A	LDRSB reg1, [reg2 + imm32]	❌	❌	❌
0x3B	LDRSB reg1, [reg2 + imm32 * imm8]	❌	❌	❌
0x3C	LDRSB reg1, [imm32]	❌	❌	❌
0x40-0x4F	Store Word Instructions
0x41	STR [reg1], reg2	✅	✅	❌
0x42	STR [reg1 + imm16], reg2	✅	✅	❌
0x43	STR [reg1 + reg2 * imm8], reg3	✅	✅	❌
0x44	STR [imm32], reg2	✅	✅	❌
0x50-0x5F	Store Half Instructions
0x51	STRH [reg1], reg2	❌	❌	❌
0x52	STRH [reg1 + imm32], reg2	❌	❌	❌
0x53	STRH [reg1 + imm32 * imm8], reg2	❌	❌	❌
0x54	STRH [imm32], reg2	❌	❌	❌
0x60-0x6F	Store Byte Instructions
0x61	STRB [reg1], reg2	❌	❌	❌
0x62	STRB [reg1 + imm32], reg2	❌	❌	❌
0x63	STRB [reg1 + imm32 * imm8], reg2	❌	❌	❌
0x64	STRB [imm32], reg2	❌	❌	❌
0x70-0x7F	Arithmetic & Logic Instructions (reg)
0x70	ADD reg1, reg2	✅	✅	❌
0x71	SUB reg1, reg2	✅	✅	❌
0x72	MUL reg1, reg2	✅	✅	❌
0x73	UDIV reg1, reg2	✅	✅	❌
0x74	SDIV reg1, reg2	✅	✅	❌
0x75	CMP reg1, reg2	❌	❌	❌
0x76	INC reg	❌	❌	❌
0x77	DEC reg	❌	❌	❌
0x78	NOT reg	✅	✅	❌
0x79	AND reg1, reg2	✅	✅	❌
0x7A	NAND reg1, reg2	✅	✅	❌
0x7B	OR reg1, reg2	✅	✅	❌
0x7C	NOR reg1, reg2	✅	✅	❌
0x7D	XOR reg1, reg2	❌	❌	❌
0x7E	XNOR reg1, reg2	❌	❌	❌
0x80-0x8F	Arithmetic & Logic Instructions (imm)
0x80	ADD reg1, imm32	❌	❌	❌
0x81	SUB reg1, imm32	❌	❌	❌
0x82	MUL reg1, imm32	❌	❌	❌
0x83	UDIV reg1, imm32	❌	❌	❌
0x84	SDIV reg1, imm32	❌	❌	❌
0x85	CMP reg1, imm32	❌	❌	❌
0x89	AND reg1, imm32	❌	❌	❌
0x8A	NAND reg1, imm32	❌	❌	❌
0x8B	OR reg1, imm32	❌	❌	❌
0x8C	NOR reg1, imm32	❌	❌	❌
0x8D	XOR reg1, imm32	❌	❌	❌
0x8E	XNOR reg1, imm32	❌	❌	❌
0x90-0x9F	Flags (set) & Shifts (reg) Instructions
0x90	STZ	✅	✅	❌
0x91	STN	✅	✅	❌
0x92	STC	✅	✅	❌
0x93	STO	✅	✅	❌
0x94	STI	🚧	❌	❌
0x98	SHL reg1, reg2	❌	❌	❌
0x99	SHR reg1, reg2	❌	❌	❌
0x9A	ROL reg1, reg2	❌	❌	❌
0x9B	ROR reg1, reg2	❌	❌	❌
0x9C	RCL reg1, reg2	❌	❌	❌
0x9D	RCR reg1, reg2	❌	❌	❌
0x9E	ASR reg1, reg2	❌	❌	❌
0xA0-0xAF	Flags (clear) & Shifts (imm) Instructions
0xA0	CLZ	✅	✅	❌
0xA1	CLN	✅	✅	❌
0xA2	CLC	✅	✅	❌
0xA3	CLO	✅	✅	❌
0xA4	CLI	🚧	❌	❌
0xA5	CLP	🚧	❌	❌
0xA8	SHL reg1, imm8	❌	❌	❌
0xA9	SHR reg1, imm8	❌	❌	❌
0xAA	ROL reg1, imm8	❌	❌	❌
0xAB	ROR reg1, imm8	❌	❌	❌
0xAC	RCL reg1, imm8	❌	❌	❌
0xAD	RCR reg1, imm8	❌	❌	❌
0xAE	ASR reg1, imm8	❌	❌	❌
0xB0-0xBF	Jump instructions (Part 1)
0xB0	JMP rel32	✅	✅	❌
0xB1	JMPN rel16	✅	✅	❌
0xB2	JMPS rel8	✅	✅	❌
0xB3	JZ rel32	✅	✅	❌
0xB4	JN rel32	✅	✅	❌
0xB5	JC rel32	✅	✅	❌
0xB6	JO rel32	✅	✅	❌
0xBB	JSZ rel32	❌	❌	❌
0xBC	JSN rel32	❌	❌	❌
0xBD	JSC rel32	❌	❌	❌
0xBE	JSO rel32	❌	❌	❌
0xC0-0xCF	Jump instructions (Part 2)
0xC0	JMPA abs32	✅	✅	❌
0xC3	JNZ rel32	✅	✅	❌
0xC4	JNN rel32	✅	✅	❌
0xC5	JNC rel32	✅	✅	❌
0xC6	JNO rel32	✅	✅	❌
0xCB	JSNZ rel32	❌	❌	❌
0xCC	JSNN rel32	❌	❌	❌
0xCD	JSNC rel32	❌	❌	❌
0xCE	JSNO rel32	❌	❌	❌
0xD0-0xDF	Jump instructions (Part 3)
0xD3	JL rel32	✅	✅	❌
0xD4	JLE rel32	✅	✅	❌
0xD5	JG rel32	✅	✅	❌
0xD6	JGE rel32	✅	✅	❌
0xDB	JSL rel8	❌	❌	❌
0xDC	JSLE rel8	❌	❌	❌
0xDD	JSG rel8	❌	❌	❌
0xDE	JSGE rel8	❌	❌	❌
0xE0-0xEF	Stack instructions
0xE0	PUSH reg	✅	✅	❌
0xE1	PUSH imm32	✅	✅	❌
0xE2	POP reg	✅	✅	❌
0xE3	PUSHF	❌	❌	❌
0xE4	POPF	❌	❌	❌
0xF0-0xFF	Subroutine instructions
0xF0	CALL rel32	✅	✅	❌
0xF1	CALLN rel16	❌	❌	❌
0xF2	CALLS rel8	❌	❌	❌
0xF3	CALL [reg]	❌	❌	❌
0xF8	RET	✅	✅	❌